Design of a high throughput electronics module for high energy physics experiments

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Chun-Jie Wang, Zhen-An Liu, Jing-Zhou Zhao and Zhao Liu. Design of a high throughput electronics module for high energy physics experiments[J]. Chinese Physics C, 2016, 40(6): 066102. doi: 10.1088/1674-1137/40/6/066102
Chun-Jie Wang, Zhen-An Liu, Jing-Zhou Zhao and Zhao Liu. Design of a high throughput electronics module for high energy physics experiments[J]. Chinese Physics C, 2016, 40(6): 066102.  doi: 10.1088/1674-1137/40/6/066102 shu
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Received: 2015-10-28
Revised: 2016-01-28
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    Supported by National Natural Science Foundation of China (11435013, 11461141011)

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Design of a high throughput electronics module for high energy physics experiments

    Corresponding author: Zhen-An Liu,
  • 1. State Key Laboratory of Particle Detection and Electronics, Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China
  • 2. University of Chinese Academy of Sciences, Beijing 100049, China
  • 3.  State Key Laboratory of Particle Detection and Electronics, Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China
Fund Project:  Supported by National Natural Science Foundation of China (11435013, 11461141011)

Abstract: High-energy physics experiments enable us to explore and understand particle properties and interactions. An increase in luminosity in the accelerator, which allows us to study particles in higher energy ranges, demands faster data transmission and processing. Aimed at this, a high throughput uTCA-compliant electronics module, based on the latest FPGAs, has been designed. It contains 48 10.0 Gb/s optical fiber input channels and 24 10.0 Gb/s optical fiber output channels, supporting up to 480 Gb/s input bandwidth and 240 Gb/s output bandwidth. It complies with the uTCA standards, providing high speed data exchange capability and functioning as a compact and key module in a trigger and DAQ system for a large experiment. A reliable 10.0 Gb/s data transmission among two boards has been verified and one functionality that merges 6 1.6 Gb/s data channels into one single 10.0 Gb/s channel has been achieved. The hardware, firmware and software together with a performance evaluation are given in this paper.

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